The present invention generally relates to semiconductor processing, and in particular to a method for forming a gate structure with a contact area wider than a base area.
Historically, gate structures having a base area with a width that is smaller than the gate contact area (e.g., F-gate and Y-gate structures) have been advantageous in several technologies. For example, MESFET, HEMT (variant of gallium arsenide field effect transistor technology) mainly used in satellite broadcasting receivers, high speed logic circuits and power modules have employed gate structures with bases smaller than the contact area. These types of devices are required in field effect transistors for operation in ultra-high frequency ranges. The advantage of employing a gate structure with a shorter gate length is that the channel of the gate is reduced resulting in an increased in speed and a decrease in power consumption. Reducing the distance over which the gate""s field effect control of the electrons in the channel reduces the parasitic resistances and capacitances that limit device speed. A shorter gate length decreases the transmit time for carriers in the channel but also increases the series resistance of the gate electrode itself, slowing down the device and degrading the frequency characteristics of the device. Providing a gate structure with a smaller base than its contact area decreases the gate channel while providing a low gate series resistance due to the wider contact area and, thus, improving the devices drive current capability and performance.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down device dimensions at submicron levels on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines and the surface geometry such as corners and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive of the subject pattern. Exposure of the coating through a photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Recent advances in CMOS transistor architecture make use of the T-gate or Y-gate structures where the polysilicon gate electrode is narrowed in the gate regions and wider on top of the gate. This is due to the ever increasing demand for scaling down semiconductor devices and scaling down power consumption requirements. However, the current methods for forming a gate structure with a contact region wider than its base suffers from shortcomings. For example, the etch process which narrows the base of the structure are known to be difficult to control especially with local pattern density. This can lead to variation in the gate width and asymmetric implant profiles. Another problem is related to manufacturing controls. The xe2x80x9cre-entrantxe2x80x9d or overhung profile prevents direct measurement of the critical gate length.
In view of the above, there is an unmet need for improvements in methodologies for formation of gate structures with contact areas that are wider than the base area.
The present invention employs a methodology for forming a T-gate structure. The methodology comprises forming a gate oxide over a silicon layer, a polysilicon layer over the gate oxide layer and an ARC layer over the polysilicon layer. A gate structure is formed by anisotropically etching the ARC layer and portions of the polysilicon layer around the gate structure. The etching of the polysilicon layer is not a complete etch and stops at a certain depth. Oxide is then formed over the polysilicon and spacers are formed outside the gate structure, for example, by performing a vertical plasma etch, thus, removing the remaining portions of the oxide. Employing the oxide as a protective hard mask, the remaining poly is etched aggressively using an isotropic etch to form undercut region under the gate structure. During the isotropic etch the polysilicon is overetched to form the undercut regions and remove the polysilicon outside the gate structure. A second pair of spacers are formed along the sidewalls of the gate structure to protect the gate structure. This is accomplished by providing an additional oxide layer and by removing the oxide outside the gate structure similar to the formation of the first spacers.
One aspect of the invention relates to a method for fabricating a T-gate structure. A structure is provided that has a silicon layer having a gate oxide layer, and a polysilicon layer over the gate oxide layer. A gate structure is formed by removing a portion of the polysilicon layer around a gate region. Undercut regions are formed in the gate structure to provide the gate structure with a base region and a contact region. The base region has a width smaller than the contact region.
Another aspect of the present invention relates to another method for fabricating a T-gate structure. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer, and an ARC layer over the polysilicon layer. A gate structure is formed by removing the ARC layer and a portion of the polysilicon layer around a gate region. Spacers are then formed around the gate structure. Undercut regions are formed in the gate structure by performing an isotropic etch to provide the gate structure with a base region and a contact region. The base region has a width smaller than the contact region.
Yet another aspect of the present invention provides for yet another method for fabricating a T-gate structure. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer, and an ARC layer over the polysilicon layer. A gate structure is formed by removing the ARC layer and a portion of the polysilicon layer around a gate region. Spacers are then formed around the gate structure. Undercut regions are formed in the gate structure by performing an Isotropic etch to provide the gate structure with a base region and a contact region. The base region has a width smaller than the contact region. The isotropic etch is performed by using a MERIE method with reactant gases of CL2(30-100 sccm) and HBr(30-100 sccm) at a power level within the range of about 300-700 W, and pressure within the range of about 10-250 mT. A second pair of spacers is then formed around the gate structure.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.